MILLENNIUM DESIGN

Signal Integrity

As bit rates increase, signal speeds get faster and distances longer, the margin for error becomes razor thin. The need for advanced Signal Integrity (SI) is apparent, which is exactly what Millennium Design supplies.

Working on the most advanced design’s in the industry with a long track record of success, we’re familiar with the importance of both pre and post design signal analysis and verification. We use our vast experience, along with the latest software tools, to provide accurate Signal Integrity analysis that will save you time and money, and ensure a successful end product. Make no mistake – SI is a crucial aspect of most any board design, and we fully understand that performance cannot be left to chance.

Millennium Design is capable of not only identifying any issues, but providing a solution as well. We can work hand in hand with your engineering and design teams, and fully support their efforts. In short, we can be as involved as you wish. And we’ll get it right the first time, every time.

Our basic SI Process is:

Phase One: Preparation for SI analysis.
This phase collects all the needed components to accurately simulate the signals in the board environment. This phase is critical to the success of the board simulations. Most of the work of this phase will be in getting the models together and input into the system. Test runs would be made to validate the models and the expected performance.
Output: A working simulation environment with all models, boards, processes in place.

Phase Two: The physics and the Reports.
This phase is where the board is made to work. Initial simulation may show violations in timing of the memory or bus structures or crosstalk that is affecting performance. This phase is highly responsive to the engineering needs and will work with the board engineer and board layout designer to modify the layout as needed to meet the client engineers goals.
Output: Reports acceptable to the Client on the performance of their board.

Phase Three: Manufacturing variation analysis of design integrity.
This phase takes the proposed vendors GUARENTEED parameters with respect to line widths, alignment, stack-up variations, material ER and Loss characteristics, and test the effect on the signal integrity of the board in production.
Output: Report for acceptability for each vendors success potential with respect to SI.

Accurate modeling of trace impedance, coupling, and frequency-dependent losses
Sweep different values for discretes, trace geometries and lengths, and driver settings
Optimal termination strategies
Timing analysis for DDR, DDR2, and DDR3
SERDES support including fast eye diagram analysis, S-parameter simulation, and BER Prediction
Advanced, exploratory via modeling
Provides an early look at likely EMC failures
Integration with the routing constraint management

Tool Sets